<div dir="ltr">I'm not an x86-64 expert, but it implies from intel docs that 64 bit immediate values are supported only for the MOV instruction:<br><br><a href="http://www.intel.com/assets/pdf/manual/253666.pdf">http://www.intel.com/assets/pdf/manual/253666.pdf</a><br>
-------------------<br>2.2.1.5 Immediates<br>In 64-bit mode, the typical size of immediate operands remains 32 bits. When the<br>operand size is 64 bits, the processor sign-extends all immediates to 64 bits prior to<br>their use.<br>
Support for 64-bit immediate operands is accomplished by expanding the semantics<br>of the existing move (MOV reg, imm16/32) instructions. These instructions (opcodes<br>B8H – BFH) move 16-bits or 32-bits of immediate data (depending on the effective<br>
operand size) into a GPR. When the effective operand size is 64 bits, these instructions<br>can be used to load an immediate into a GPR. A REX prefix is needed to override<br>the 32-bit default operand size to a 64-bit operand size.<br>
For example:<br>48 B8 8877665544332211 MOV RAX,1122334455667788H<br>-------------------<br>Udi<br><br><div class="gmail_quote">On Fri, Feb 4, 2011 at 9:02 AM, Gilboa Davara <span dir="ltr"><<a href="mailto:gilboad@gmail.com">gilboad@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">Hello all,<br>
<br>
I'm trying to pass the following command inside GCC inline assembly<br>
block (which targets x86_64 kernel and usermode).<br>
<br>
asm volatile<br>
{<br>
...<br>
"andq $0x5555555555555555, %%r11 ;"<br>
...<br>
}<br>
<br>
And getting the following error:<br>
'Error: operand type mismatch for `and''<br>
<br>
The 32bit version of this code (which uses $0x55555555 constant value)<br>
works just fine.<br>
Shaving ~4 digits off the constant value, seems to working as well.<br>
<br>
So, any idea how I can force-feed 64bit hex values into 64bit inline<br>
assembly?<br>
<br>
- Gilboa<br>
<br>
<br>
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</blockquote></div><br></div>